![]() Moreover, SMU power draw regularly exceeds even that number, without PBO, on full load for my I just want to know if the SMU wattage readings under the CPU sensors in HWInfo are skewed because of this, or if it just affects the CPU's boost algorithms internally. PPT is already considerably higher than TDP, approx 88W for 65W and 142W for 105W parts. Thus it makes a lot of sense why this misreporting would be a problem. Ryzen CPUs all abide by PPT, TDC and EDC for their power and current limits. Last AM4 CPU that I can think of actually kinda abided by TDP is the 2700, which actually sipped power but a little too much. A suggested workload to get a stable and reproducable deviation metric is Cinebench R20 NT, with the HWiNFO sample rate set to less or equal to 1000ms. That is due to the typical measurement accuracy of the VRM controller telemetry, and also due to the highly advanced and fast power management on Ryzen CPUs, that not only result in extremely low idle, but also in extremely rapidly changing power consumption. Obviously, the figure can be greater than 100%, but for the obvious reasons it rarely isĪs stated before, this metric is only valid during a relatively stable near-full-load condition. So, if you see an average value that is significantly lower than ~ 95% there is most likely intentional biasing going on. A ballpark for a threshold, where the readings become suspicious is around ±5%. When the motherboard manufacturer has both properly calibrated and declared the reference value, the reported figure should be pretty close to 100% under a stable, near-full-load scenario. The displayed figure is a percentage, with 100.0% being the completely unbiased baseline. HWiNFO will display "Power Reporting Deviation" metric under the CPUs enhanced sensors.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |